adding physical layout scripts
This commit is contained in:
parent
9a216710a1
commit
2cea2debdb
4
rect2gds.sh
Executable file
4
rect2gds.sh
Executable file
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#!/bin/bash
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./rect2lef.py -Tsky130 $1.rect $1.lef layermap.txt
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strm2gds -d 20 --lefdef-map layermap.txt $1.lef $1.gds
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241
rect2lef.py
Executable file
241
rect2lef.py
Executable file
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#!/usr/bin/python3
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import os
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import sys
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def stripComments(line):
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escape = False
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inString = False
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for i, c in enumerate(line):
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if not escape and (c == "\"" or c == "\'"):
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inString = not inString
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elif inString and c == "\\":
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escape = not escape
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elif not inString and c == "#":
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return line[0:i]
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else:
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escape = False
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return line
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def loadActConf(path):
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result = dict()
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stack = [result]
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with open(path, "r") as fptr:
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for number, line in enumerate(fptr):
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if "#" in line:
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line = line[0:line.index("#")]
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args = [arg.strip() for arg in line.strip().split(" ")]
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if len(args) > 0:
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if args[0] == "include":
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result = result | loadActConf(args[1][1:-1])
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elif args[0] == "begin":
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stack[-1][args[1]] = dict()
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stack.append(stack[-1][args[1]])
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elif args[0] == "end":
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stack.pop()
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elif args[0] == "string":
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stack[-1][args[1]] = args[2][1:-1]
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elif args[0] == "int":
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stack[-1][args[1]] = int(args[2])
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elif args[0] == "real":
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stack[-1][args[1]] = float(args[2])
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elif args[0] == "int_table":
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stack[-1][args[1]] = [int(arg) for arg in args[2:]]
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elif args[0] == "string_table":
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stack[-1][args[1]] = [arg[1:-1] for arg in args[2:]]
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return result
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def queryGDS(conf, rectLayer):
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gds = []
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gds_bloat = []
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if rectLayer in conf["materials"]:
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if "gds" in conf["materials"][rectLayer]:
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gds = conf["materials"][rectLayer]["gds"]
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if "gds_bloat" in conf["materials"][rectLayer]:
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gds_bloat = conf["materials"][rectLayer]["gds_bloat"]
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else:
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if rectLayer+"_gds" in conf["materials"]["metal"]:
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gds = conf["materials"]["metal"][rectLayer+"_gds"]
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if rectLayer+"_gds_bloat" in conf["materials"]["metal"]:
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gds_bloat = conf["materials"]["metal"][rectLayer+"_gds_bloat"]
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return zip(gds, gds_bloat)
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TAP, FILL, CELL, BLOCK = range(4)
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class Rect:
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def __init__(self, label, layer, bounds, hint="", isInput=False, isOutput=False):
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self.label = label
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self.layer = layer
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self.bounds = [int(bound) for bound in bounds]
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self.hint = hint
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self.isInput = isInput
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self.isOutput = isOutput
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def isIn(searches, string):
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for search in searches:
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if search in string:
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return True
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return False
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class Cell:
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def __init__(self, name, kind, bbox, rects):
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self.name = name
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self.kind = kind
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self.bbox = bbox
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self.rects = rects
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def readCell(path):
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name = os.path.splitext(os.path.basename(path))[0]
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kind = BLOCK
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if "welltap" in name.lower():
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kind = TAP
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elif "fill" in name.lower():
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kind = FILL
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elif "cell" in name.lower():
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kind = CELL
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# left, bottom, right, top
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bbox = [0, 0, 1, 1]
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rects = []
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with open(path, "r") as rf:
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for number, line in enumerate(rf):
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args = [arg.strip() for arg in line.split(" ")]
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if args[0] == "bbox":
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bbox = [int(arg) for arg in args[1:]]
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else:
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isInput = (args[0] == "inrect")
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isOutput = (args[0] == "outrect")
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hint = ""
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if len(args) >= 8:
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hint = args[7]
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rects.append(Rect(args[1], args[2], [int(arg) for arg in args[3:7]], hint, isInput, isOutput))
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return Cell(name, kind, bbox, rects)
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def writeLayerMap(path, conf):
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layers = zip(conf["gds"]["layers"], conf["gds"]["major"], conf["gds"]["minor"])
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with open(path, "w") as fptr:
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for layer in layers:
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name, purpose = layer[0].rsplit(".", 1)
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if "via" in name and purpose in ["drawing", "dg", "drw"]:
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print(f"{name} VIA {layer[1]} {layer[2]}", file=fptr)
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elif purpose in ["drawing", "dg", "drw"]:
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print(f"{name} LEFOBS {layer[1]} {layer[2]}", file=fptr)
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elif purpose in ["label", "ll", "lbl"]:
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print(f"NAME {name}/PINNAME {layer[1]} {layer[2]}", file=fptr)
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print(f"NAME {name}/PIN {layer[1]} {layer[2]}", file=fptr)
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print(f"NAME {name}/LEFPINNAME {layer[1]} {layer[2]}", file=fptr)
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print(f"NAME {name}/LEFPIN {layer[1]} {layer[2]}", file=fptr)
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elif purpose in ["net", "nt"]:
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print(f"{name} NET {layer[1]} {layer[2]}", file=fptr)
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elif purpose in ["pin", "pin1", "pn"]:
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print(f"{name} PIN,LEFPIN {layer[1]} {layer[2]}", file=fptr)
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elif purpose in ["blockage", "be", "blo"]:
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print(f"{name} BLOCKAGE {layer[1]} {layer[2]}", file=fptr)
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if "prb" in name.lower():
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print(f"DIEAREA ALL {layer[1]} {layer[2]}", file=fptr)
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def writeLEF(path, conf, cell):
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scale = conf["general"]["scale"]
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numMetals = conf["general"]["metals"]
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with open(path, "w") as fptr:
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print(f"MACRO {cell.name}", file=fptr)
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if cell.kind == TAP:
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print("CLASS CORE WELLTAP ;", file=fptr)
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elif cell.kind == FILL:
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print("CLASS CORE SPACER ;", file=fptr)
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elif cell.kind == CELL:
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print("CLASS CORE ;", file=fptr)
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else:
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print("CLASS BLOCK ;", file=fptr)
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print(f"\tORIGIN {-cell.bbox[0]*scale} {-cell.bbox[1]*scale} ;", file=fptr)
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print(f"\tFOREIGN {cell.name} {cell.bbox[0]*scale} {cell.bbox[1]*scale} ;", file=fptr)
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print(f"\tSIZE {(cell.bbox[2]-cell.bbox[0])*scale} BY {(cell.bbox[3]-cell.bbox[1])*scale} ;", file=fptr)
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print(f"\tSYMMETRY X Y ;", file=fptr)
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if cell.kind in [FILL, TAP, CELL]:
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print("\tSITE CoreSite ;", file=fptr)
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for rect in cell.rects:
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if rect.isInput or rect.isOutput:
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direction = "INOUT"
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if not rect.isInput:
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direction = "OUTPUT"
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elif not rect.isOutput:
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direction = "INPUT"
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print(f"\tPIN {rect.label}", file=fptr)
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if isIn(["vnsub", "vpsub", "vddsub", "vsssub", "vddb", "vssb"], rect.label.lower()):
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print("\t\tDIRECTION INOUT ;", file=fptr)
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print("\t\tUSE POWER ;", file=fptr)
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elif isIn(["vdd", "pwr"], rect.label.lower()):
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print("\t\tDIRECTION INOUT ;", file=fptr)
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print("\t\tUSE POWER ;", file=fptr)
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if cell.kind in [FILL, TAP, CELL]:
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print("\t\tSHAPE ABUTMENT ;", file=fptr)
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elif isIn(["gnd", "vss"], rect.label.lower()):
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print("\t\tDIRECTION INOUT ;", file=fptr)
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print("\t\tUSE GROUND ;", file=fptr)
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if cell.kind in [FILL, TAP, CELL]:
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print("\t\tSHAPE ABUTMENT ;", file=fptr)
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else:
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print(f"\t\tDIRECTION {direction} ;", file=fptr)
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print(f"\t\tUSE SIGNAL ;", file=fptr)
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print("\t\tPORT", file=fptr)
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gds = queryGDS(conf, rect.layer)
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for layer, bloat in gds:
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name, purpose = layer.rsplit(".", 1)
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print(f"\t\t\tLAYER {name} ;", file=fptr)
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print(f"\t\t\t\tRECT {(rect.bounds[0]-bloat)*scale} {(rect.bounds[1]-bloat)*scale} {(rect.bounds[2]+bloat)*scale} {(rect.bounds[3]+bloat)*scale} ;", file=fptr)
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print("\t\tEND", file=fptr)
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print(f"\tEND {rect.label}", file=fptr)
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print("\tOBS", file=fptr)
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for rect in cell.rects:
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#if not rect.isInput and not rect.isOutput:
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gds = queryGDS(conf, rect.layer)
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for layer, bloat in gds:
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name, purpose = layer.rsplit(".", 1)
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print(f"\t\tLAYER {name} ;", file=fptr)
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print(f"\t\t\tRECT {(rect.bounds[0]-bloat)*scale} {(rect.bounds[1]-bloat)*scale} {(rect.bounds[2]+bloat)*scale} {(rect.bounds[3]+bloat)*scale} ;", file=fptr)
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print("\tEND", file=fptr)
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print(f"END {cell.name}", file=fptr)
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print("", file=fptr)
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def print_help():
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print("Usage: rect2lef.py [options] <input.rect> <output.lef> [output.layermap]")
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print("\t-T<tech>\tidentify the technology used for this translation.")
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if __name__ == "__main__":
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if len(sys.argv) <= 2 or sys.argv[1] == '--help' or sys.argv[1] == '-h':
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print_help()
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else:
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rectPath = None
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lefPath = None
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lmPath = None
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techName = "sky130"
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actHome = os.environ.get('ACT_HOME', "/opt/cad")
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for arg in sys.argv[1:]:
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if arg[0] == '-':
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if arg[1] == 'T':
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techName = arg[2:]
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else:
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print(f"error: unrecognized option '{arg}'")
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print("")
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print_help()
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sys.exit()
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elif not rectPath:
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rectPath = arg
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elif not lefPath:
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lefPath = arg
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elif not lmPath:
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lmPath = arg
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conf = loadActConf(actHome + "/conf/" + techName + "/layout.conf")
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if rectPath and lefPath:
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cell = readCell(rectPath)
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writeLEF(cell.name + ".lef", conf, cell)
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if lmPath:
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writeLayerMap(lmPath, conf)
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547
spi2act.py
Executable file
547
spi2act.py
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#!/usr/bin/python3
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import sys
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from math import trunc
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# lvtnfet d g s b
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#
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class Transistor:
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def __init__(self,
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inst,
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kind,
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gate,
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source,
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drain,
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bulk,
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width = 1,
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length = 1):
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self.inst = inst
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self.kind = kind
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self.gate = gate
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self.source = source
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self.drain = drain
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self.bulk = bulk
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self.width = width
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self.length = length
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self.shared_source = list()
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self.shared_drain = list()
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def emit(self, sources, tab = ''):
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if self.drain in sources or self.drain[0] == '@':
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self.flip()
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if self.source in sources:
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if self.kind == 'n':
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fmt = tab + '{gate}<{width:.1f},{length:.1f}> -> {drain}-'
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elif self.kind == 'p':
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fmt = tab + '~{gate}<{width:.1f},{length:.1f}> -> {drain}+'
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elif self.source[0] == '@':
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if self.kind == 'n':
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fmt = tab + '~{source} & {gate}<{width:.1f},{length:.1f}> -> {drain}-'
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elif self.kind == 'p':
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fmt = tab + '{source} & ~{gate}<{width:.1f},{length:.1f}> -> {drain}+'
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else:
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fmt = tab + 'pass{kind}<{width:.1f},{length:.1f}>({gate}, {source}, {drain})'
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#fmt = tab + '{gate}<{width:.1f},{length:.1f}> -> {drain} := {source}'
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return fmt.format(
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kind=self.kind,
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width=trunc(self.width),
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length=trunc(self.length),
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gate=self.gate,
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source=self.source,
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drain=self.drain)
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def emit_expr(self):
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return '{kind}{gate}<{width:.1f},{length:.1f}>'.format(
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kind = '~' if self.kind == 'p' else '',
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gate = self.gate,
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width = trunc(self.width),
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length = trunc(self.length))
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def ports(self):
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result = [self.bulk, self.gate]
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if self.source[0] != '@':
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result.append(self.source)
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if self.drain[0] != '@':
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result.append(self.drain)
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return list(set(result))
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def gates(self):
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return [self.gate]
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def flip(self):
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self.source,self.drain = self.drain,self.source
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self.shared_source,self.shared_drain = self.shared_drain,self.shared_source
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class Expr:
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def __init__(self,
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op,
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kind,
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source,
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drain,
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bulk = '',
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devs = None):
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self.op = op
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self.kind = kind
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self.source = source
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self.drain = drain
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self.bulk = bulk
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if devs:
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self.devs = devs
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else:
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self.devs = list()
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self.shared_source = list()
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self.shared_drain = list()
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def emit_expr(self):
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return (' ' + self.op + ' ').join([
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'(' + dev.emit_expr() + ')'
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if isinstance(dev, Expr) and dev.op == '|'
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else dev.emit_expr()
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for dev in self.devs])
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def emit(self, sources, tab = ''):
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if self.drain in sources or self.drain[0] == '@':
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self.flip()
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if self.source in sources:
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if self.kind == 'n':
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return tab + self.emit_expr() + ' -> ' + self.drain + '-'
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elif self.kind == 'p':
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return tab + self.emit_expr() + ' -> ' + self.drain + '+'
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elif self.source[0] == '@':
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if self.kind == 'n':
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return tab + '~' + self.source + ' & (' + self.emit_expr() + ') -> ' + self.drain + '-'
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elif self.kind == 'p':
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return tab + self.source + ' & (' + self.emit_expr() + ') -> ' + self.drain + '+'
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else:
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return '\n'.join([dev.emit(sources, tab) for dev in self.devs])
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#return tab + self.emit_expr() + ' -> ' + self.drain + ' := ' + self.source
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def gates(self):
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result = list()
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for dev in self.devs:
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result += dev.gates()
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return list(set(result))
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def ports(self):
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result = [self.bulk]
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if self.source[0] != '@':
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result.append(self.source)
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if self.drain[0] != '@':
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result.append(self.drain)
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result += self.gates()
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return list(set(result))
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def flip(self):
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self.source,self.drain = self.drain,self.source
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self.shared_source,self.shared_drain = self.shared_drain,self.shared_source
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for dev in self.devs:
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dev.flip()
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self.devs.reverse()
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class Instance:
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def __init__(self,
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name,
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typename,
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ports = None):
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self.name = name
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self.typename = typename
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if ports:
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self.ports = ports
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else:
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self.ports = list()
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def emit(self, tab = ''):
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if self.ports:
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return tab + '{typename} {name}({ports});'.format(
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typename = self.typename,
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name = self.name,
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ports = ', '.join(self.ports))
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else:
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return tab + self.typename + ' ' + self.name + ';'
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def can_merge(left, right, sources):
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return left == right or (left in sources or left and left[0] == '@') and (right in sources or right and right[0] == '@')
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class Process:
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def __init__(self,
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name,
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ports = None,
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nets = None,
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devs = None,
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use_globals = False):
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self.name = name
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self.use_globals = use_globals
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if self.use_globals:
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self.vdd = 'g.Vdd'
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self.gnd = 'g.GND'
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self.vdds = 'g.vpsub'
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self.gnds = 'g.vnsub'
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else:
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self.vdd = None
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self.gnd = None
|
||||
self.vdds = None
|
||||
self.gnds = None
|
||||
|
||||
self.ports = list()
|
||||
self.add_ports(ports)
|
||||
self.nets = list()
|
||||
self.add_nets(nets)
|
||||
self.devs = list()
|
||||
self.add_devs(devs)
|
||||
self.insts = list()
|
||||
|
||||
@property
|
||||
def sources(self):
|
||||
return [x for x in [self.vdd, self.gnd, self.vdds, self.gnds] if not x is None]
|
||||
|
||||
def check(self, names):
|
||||
if names is not None:
|
||||
if isinstance(names, list):
|
||||
result = list()
|
||||
for name in names:
|
||||
result.extend(self.check(name))
|
||||
return result
|
||||
else:
|
||||
if 'vdds' in names.lower() or 'vpb' in names.lower() or 'vpsub' in names.lower() or names == self.vdds:
|
||||
if not self.vdds:
|
||||
self.vdds = names
|
||||
return [self.vdds]
|
||||
elif 'gnds' in names.lower() or 'vnb' in names.lower() or 'vnsub' in names.lower() or names == self.gnds:
|
||||
if not self.gnds:
|
||||
self.gnds = names
|
||||
return [self.gnds]
|
||||
elif 'vdd' in names.lower() or 'pwr' in names.lower() or names == self.vdd:
|
||||
if not self.vdd:
|
||||
self.vdd = names
|
||||
return [self.vdd]
|
||||
elif 'gnd' in names.lower() or names == self.gnd:
|
||||
if not self.gnd:
|
||||
self.gnd = names
|
||||
return [self.gnd]
|
||||
else:
|
||||
return [names.replace("#","")]
|
||||
return []
|
||||
|
||||
def add_ports(self, ports):
|
||||
if self.use_globals:
|
||||
self.ports.extend([x for x in self.check(ports) if x not in self.sources])
|
||||
else:
|
||||
self.ports.extend(self.check(ports))
|
||||
|
||||
def add_nets(self, nets):
|
||||
self.nets.extend([x for x in self.check(nets) if x not in self.sources])
|
||||
|
||||
def check_devs(self, devs):
|
||||
if devs is not None:
|
||||
if isinstance(devs, list):
|
||||
result = list()
|
||||
for dev in devs:
|
||||
result.extend(self.check_devs(dev))
|
||||
return result
|
||||
else:
|
||||
devs.source = self.check(devs.source)[0]
|
||||
devs.drain = self.check(devs.drain)[0]
|
||||
devs.bulk = self.check(devs.bulk)[0]
|
||||
if isinstance(devs, Transistor):
|
||||
devs.gate = self.check(devs.gate)[0]
|
||||
if isinstance(devs, Expr):
|
||||
devs.devs = self.check_devs(devs.devs)
|
||||
return [devs]
|
||||
return []
|
||||
|
||||
def add_devs(self, devs):
|
||||
self.devs.extend(self.check_devs(devs))
|
||||
|
||||
def add_insts(self, insts):
|
||||
if insts is not None:
|
||||
if isinstance(insts, list):
|
||||
result = list()
|
||||
for inst in insts:
|
||||
self.add_inst(inst)
|
||||
else:
|
||||
insts.ports = self.check(insts.ports)
|
||||
self.insts.append(insts)
|
||||
|
||||
def build_nets(self):
|
||||
for dev in self.devs:
|
||||
for port in dev.ports():
|
||||
if port not in self.ports and port not in self.nets and port not in self.sources:
|
||||
self.nets.append(port)
|
||||
|
||||
def build_AND(self):
|
||||
nets = self.nets + [x for x in self.ports if x not in self.sources]
|
||||
for net in nets:
|
||||
source = list()
|
||||
drain = list()
|
||||
for dev in self.devs:
|
||||
if dev.source == net:
|
||||
source.append(dev)
|
||||
if dev.drain == net:
|
||||
drain.append(dev)
|
||||
|
||||
lst = list()
|
||||
if len(source) == 1 and len(drain) == 1 and source[0].bulk == drain[0].bulk and source[0].kind == drain[0].kind:
|
||||
lst = drain+source
|
||||
elif len(source) == 2 and len(drain) == 0 and source[0].bulk == source[1].bulk and source[0].kind == source[1].kind:
|
||||
source.sort(key=lambda dev: dev.drain not in [self.vdd, self.gnd])
|
||||
source[0].flip()
|
||||
lst = source
|
||||
elif len(source) == 0 and len(drain) == 2 and drain[0].bulk == drain[1].bulk and drain[0].kind == drain[1].kind:
|
||||
drain.sort(key=lambda dev: dev.source not in [self.vdd, self.gnd])
|
||||
drain[1].flip()
|
||||
lst = drain
|
||||
|
||||
if lst:
|
||||
self.devs.remove(lst[0])
|
||||
self.devs.remove(lst[1])
|
||||
self.nets.remove(net)
|
||||
devs = list()
|
||||
|
||||
if isinstance(lst[0], Expr) and lst[0].op == '&':
|
||||
devs += lst[0].devs
|
||||
else:
|
||||
devs.append(lst[0])
|
||||
|
||||
if isinstance(lst[1], Expr) and lst[1].op == '&':
|
||||
devs += lst[1].devs
|
||||
else:
|
||||
devs.append(lst[1])
|
||||
|
||||
self.devs.append(Expr('&', lst[0].kind, lst[0].source, lst[1].drain, lst[0].bulk, devs))
|
||||
|
||||
def build_OR(self):
|
||||
nets = self.nets + [x for x in self.ports if x not in self.sources] + self.sources
|
||||
for source in nets:
|
||||
for drain in nets:
|
||||
devs = dict()
|
||||
for dev in self.devs:
|
||||
if can_merge(dev.source, source, [self.vdd, self.gnd]) and dev.drain == drain:
|
||||
if dev.bulk not in devs:
|
||||
devs[dev.bulk] = [[dev], [], dev.kind]
|
||||
else:
|
||||
devs[dev.bulk][0].append(dev)
|
||||
elif can_merge(dev.drain, source, [self.vdd, self.gnd]) and dev.source == drain:
|
||||
if dev.bulk not in devs:
|
||||
devs[dev.bulk] = [[], [dev], dev.kind]
|
||||
else:
|
||||
devs[dev.bulk][1].append(dev)
|
||||
|
||||
for bulk,dev in devs.items():
|
||||
if len(dev[0]) + len(dev[1]) > 1:
|
||||
for d in dev[0]:
|
||||
self.devs.remove(d)
|
||||
for d in dev[1]:
|
||||
self.devs.remove(d)
|
||||
d.flip()
|
||||
|
||||
self.devs.append(Expr('|', dev[2], source, drain, bulk, dev[0] + dev[1]))
|
||||
|
||||
def build_shared(self):
|
||||
nets = self.nets + [x for x in self.ports if x not in self.sources]
|
||||
for net in nets:
|
||||
source = list()
|
||||
drain = list()
|
||||
gate = list()
|
||||
for dev in self.devs:
|
||||
if dev.source == net:
|
||||
source.append(dev)
|
||||
if dev.drain == net:
|
||||
drain.append(dev)
|
||||
if net in dev.gates():
|
||||
gate.append(dev)
|
||||
|
||||
if not gate and len(source) > 1 and len(drain) == 1 and source[0].bulk == drain[0].bulk and source[0].kind == drain[0].kind:
|
||||
if net in self.nets:
|
||||
self.nets.remove(net)
|
||||
for dev in source:
|
||||
dev.source = '@' + dev.source
|
||||
dev.shared_source = source
|
||||
for dev in drain:
|
||||
dev.drain = '@' + dev.drain
|
||||
dev.shared_drain = drain
|
||||
|
||||
def build_exprs(self):
|
||||
done_shared = False
|
||||
while not done_shared:
|
||||
done_shared = True
|
||||
|
||||
l = len(self.devs)+1
|
||||
while len(self.devs) < l:
|
||||
l = len(self.devs)
|
||||
self.build_AND()
|
||||
self.build_OR()
|
||||
if len(self.devs) < l:
|
||||
done_shared = False
|
||||
|
||||
self.build_shared()
|
||||
|
||||
self.devs.sort(key=lambda dev: [dev.drain, dev.kind])
|
||||
|
||||
def emit(self, tab = ''):
|
||||
result = [tab + 'export defproc {name}({glob}bool {ports}) {{'.format(
|
||||
name = self.name,
|
||||
glob = "globals g; " if self.use_globals else "",
|
||||
ports = ', '.join(self.ports))]
|
||||
|
||||
if self.nets:
|
||||
result += [tab + '\tbool ' + ', '.join(self.nets) + ';\n']
|
||||
|
||||
for inst in self.insts:
|
||||
result.append(inst.emit(tab + '\t'))
|
||||
|
||||
result.append('')
|
||||
result.append(tab + '\tprs <{vdd}, {gnd} | {vdds}, {gnds}> {{'.format(
|
||||
vdd = self.vdd,
|
||||
gnd = self.gnd,
|
||||
vdds = self.vdds,
|
||||
gnds = self.gnds))
|
||||
|
||||
if self.devs:
|
||||
for dev in self.devs:
|
||||
devstr = dev.emit([self.vdd, self.gnd], tab + '\t\t')
|
||||
if devstr.strip():
|
||||
result.append(devstr)
|
||||
|
||||
result.append(tab + '\t}')
|
||||
result.append(tab + '}\n')
|
||||
return result
|
||||
|
||||
def interpret_length(length):
|
||||
if length[-1] == 'm':
|
||||
return float(length[0:-1])*1e-3
|
||||
elif length[-1] == 'u':
|
||||
return float(length[0:-1])*1e-6
|
||||
elif length[-1] == 'n':
|
||||
return float(length[0:-1])*1e-9
|
||||
elif length[-1] == 'p':
|
||||
return float(length[0:-1])*1e-12
|
||||
elif length[-1] == 'f':
|
||||
return float(length[0:-1])*1e-15
|
||||
return float(length)
|
||||
|
||||
def print_help():
|
||||
print("Usage: spi2act.py [options] <lambda> <spice file>")
|
||||
print("\t--globals,-g\tbundles the power rails into a globals structure.")
|
||||
print("")
|
||||
print("Tech Lambda")
|
||||
print("ibm10lp 0.025e-6")
|
||||
print("ibm12soi 0.019e-6")
|
||||
print("ibm28lp 0.015e-6")
|
||||
print("ibm9lp 0.05e-6")
|
||||
print("ibm9sf 0.04e-6")
|
||||
print("sam28lp 0.015e-6")
|
||||
print("st28soi 0.015e-6")
|
||||
print("tsmc65 0.03e-6")
|
||||
print("xlp2 0.075e-6")
|
||||
|
||||
if __name__ == "__main__":
|
||||
if len(sys.argv) <= 2 or sys.argv[1] == '--help' or sys.argv[1] == '-h':
|
||||
print_help()
|
||||
else:
|
||||
myproc = None
|
||||
scale = None
|
||||
in_path = None
|
||||
use_globals = False
|
||||
swap_source_drain = False
|
||||
for arg in sys.argv[1:]:
|
||||
if arg[0] == '-':
|
||||
if arg == '--globals' or arg == '-g':
|
||||
use_globals = True
|
||||
elif arg == '--swap' or arg == '-s':
|
||||
swap_source_drain = True
|
||||
else:
|
||||
print("error: unrecognized option '{arg}'".format(arg=arg))
|
||||
print("")
|
||||
print_help()
|
||||
sys.exit()
|
||||
elif not scale:
|
||||
scale = float(arg)
|
||||
elif not in_path:
|
||||
in_path = arg
|
||||
|
||||
if use_globals:
|
||||
print("import \"globals.act\";")
|
||||
print("")
|
||||
|
||||
with open(in_path, "r") as lines:
|
||||
for number, line in enumerate(lines):
|
||||
line = line.strip()
|
||||
if line:
|
||||
if '.subckt' in line.lower():
|
||||
subckt = line.split(' ')
|
||||
myproc = Process(name = subckt[1], ports = subckt[2:], use_globals = use_globals)
|
||||
elif '.ends' in line.lower():
|
||||
if myproc:
|
||||
myproc.build_nets()
|
||||
myproc.build_exprs()
|
||||
print('\n'.join(myproc.emit()))
|
||||
myproc = None
|
||||
else:
|
||||
print("error: dangling '.ends' on line " + str(number))
|
||||
sys.exit()
|
||||
elif line[0].lower() != '*':
|
||||
# this is a device definition
|
||||
line = line.replace(" =", "=")
|
||||
line = line.replace("= ", "=")
|
||||
devs = line.split(' ')
|
||||
attrs = dict()
|
||||
ports = list()
|
||||
instname = None
|
||||
typename = None
|
||||
for dev in devs:
|
||||
if '=' in dev:
|
||||
attr = dev.split('=')
|
||||
attrs[attr[0]] = attr[1]
|
||||
else:
|
||||
port = dev.split(':')
|
||||
ports.append(port[0])
|
||||
instname = ports[0]
|
||||
ports = ports[1:]
|
||||
|
||||
if line[0].lower() == 'x':
|
||||
# this device is a subckt instantiation
|
||||
typename = ports[-1]
|
||||
ports = ports[:-1]
|
||||
|
||||
if myproc and 'fet' in typename:
|
||||
# this subckt is a mosfet
|
||||
myproc.add_devs(Transistor(
|
||||
inst = instname,
|
||||
kind = 'p' if 'pfet' in typename else 'n',
|
||||
# .subckt sky130_fd_pr__nfet_01v8 d g s b
|
||||
gate = ports[1],
|
||||
source = ports[2] if not swap_source_drain else ports[0],
|
||||
drain = ports[0] if not swap_source_drain else ports[2],
|
||||
bulk = ports[3],
|
||||
width = interpret_length(attrs['w'])/scale,
|
||||
length = interpret_length(attrs['l'])/scale))
|
||||
elif myproc and 'diode' not in typename:
|
||||
myproc.add_insts(Instance(
|
||||
name = instname,
|
||||
typename = typename,
|
||||
ports = ports))
|
||||
elif line[0].lower() == 'm':
|
||||
# this device is a transistor instantiation
|
||||
typename = ports[-1]
|
||||
ports = ports[:-1]
|
||||
if 'w' not in attrs or 'l' not in attrs:
|
||||
print(line)
|
||||
|
||||
# this subckt is a mosfet
|
||||
myproc.add_devs(Transistor(
|
||||
inst = instname,
|
||||
kind = 'p' if 'pfet' in typename else 'n',
|
||||
gate = ports[1],
|
||||
source = ports[2] if not swap_source_drain else ports[0],
|
||||
drain = ports[0] if not swap_source_drain else ports[2],
|
||||
bulk = ports[3],
|
||||
width = interpret_length(attrs['w'])/scale,
|
||||
length = interpret_length(attrs['l'])/scale))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user